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| ? 2008 microchip technology inc. ds11177e-page 1 mcp606/7/8/9 features ? low input offset voltage: 250 v (maximum) ? rail-to-rail output ? low input bias current: 80 pa (maximum at +85c) ? low quiescent current: 25 a (maximum) ? power supply voltage: 2.5v to 6.0v ? unity-gain stable ? chip select (cs ) capability: mcp608 ? industrial temperature range: -40c to +85c ? no phase reversal ? available in single, dual and quad packages typical applications ? battery power instruments ? high-impedance applications ? strain gauges ? medical instruments ? test equipment design aids ? spice macro models ? filterlab ? software ? mindi? circuit designer & simulator ? analog demonstration and evaluation boards ? application notes typical application description the mcp606/7/8/9 family of operational amplifiers (op amps) from microchip technology inc. are unity-gain stable with low offset voltage (250 v, maximum). performance characteristics include rail-to-rail output swing capability and low input bias current (80 pa at +85c, maximum). these feat ures make this family of op amps well suited for single-supply, precision, high-impedance, battery-powered applications. the single is available in standard 8-lead pdip, soic and tssop packages, as well as in a sot-23-5 package. the single mcp608 with chip select (cs ) is offered in the standard 8-lead pdip, soic and tssop packages. the dual mcp607 is offered in the standard 8-lead pdip, soic and tssop packages. finally, the quad mcp609 is offered in the standard 14-lead pdip, soic and tssop packages. all devices are fully specified from -40c to +85c, with power supplies from 2.5v to 6.0v. package types low-side battery current sensor r f to load 2.5v r g mcp606 5k 50 k to load v out r sen 10 (v lm ) (v lp ) i l to 6.0v v out v lm i + l r sen r f r g ? () = v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc nc nc mcp606 pdip, soic,tssop mcp607 pdip, soic,tssop mcp608 pdip, soic,tssop mcp609 pdip, soic,tssop mcp606 sot-23-5 v in + v ss v in ? 1 2 3 5 4 v dd v out v ina + v ina ? v ss v outb v inb ? 1 2 3 4 8 7 6 5 v inb + v dd v outa v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc cs nc v ina + v ina ? v dd v ind ? v ind + 1 2 3 4 14 13 12 11 v ss v outd v outa v inb ? v inb + v outb v inc + v inc ? 5 6 7 10 9 8 v outc 2.5v to 6.0v micropower cmos op amp
mcp606/7/8/9 ds11177e-page 2 ? 2008 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd ?v ss ........................................................................7.0v current at input pins ....................................................2 ma analog inputs (v in +, v in ?) ?? ........ v ss ?1.0vtov dd +1.0v all other inputs and outputs ......... v ss ? 0.3v to v dd +0.3v difference input voltage ...................................... |v dd ?v ss | output short circuit current .................................continuous current at output and supply pins ............................30 ma storage temperature..................................?65 c to +150 c maximum junction temperature (t j ) ........................ .+150 c esd protection on all pins (hbm; mm) .............. 3 kv; 200v ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rati ng only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. exposure to maximu m rating conditions for extended periods may affect device reliability. ?? see section 4.1.2 ?input voltage and current limits? . dc characteristics electrical characteristics: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss =gnd, t a =+25c, v cm =v dd /2, v out v dd /2, v l = v dd /2, r l = 100 k to v l , and cs is tied low (refer to figure 1-2 and figure 1-3 ). parameters sym min typ max units conditions input offset input offset voltage v os -250 ? +250 v input offset drift with temperature v os / t a ?1.8?v/ct a = -40c to +85c power supply rejection ratio psrr 80 93 ? db input bias current and impedance input bias current i b ?1?pa at temperature i b ??80pat a = +85c input offset bias current i os ?1?pa common mode input impedance z cm ?10 13 ||6 ? ||pf differential input impedance z diff ?10 13 ||6 ? ||pf common mode common mode input range v cmr v ss ?0.3 v dd ? 1.1 v cmrr 75 db common mode rejection ratio cmrr 75 91 ? db v dd = 5v, v cm = -0.3v to 3.9v open-loop gain dc open-loop gain (large-signal) a ol 105 121 ? db r l = 25 k to v l , v out = 50 mv to v dd ?50mv dc open-loop gain (large-signal) a ol 100 118 ? db r l = 5 k to v l , v out = 0.1v to v dd ?0.1v output maximum output voltage swing v ol , v oh v ss +15 ? v dd ?20 mv r l = 25 k to v l , 0.5v input overdrive v ol , v oh v ss +45 ? v dd ?60 mv r l = 5 k to v l , 0.5v input overdrive linear output voltage range v out v ss +50 ? v dd ?50 mv r l = 25 k to v l , a ol 105 db v out v ss +100 ? v dd ? 100 mv r l = 5 k to v l , a ol 100 db output short circuit current i sc ?7?mav dd = 2.5v i sc ?17?mav dd = 5.5v power supply supply voltage v dd 2.5 ? 6.0 v quiescent current per amplifier i q ? 18.7 25 a i o = 0 note 1: all parts with date codes november 2007 and la ter have been screened to ensure operation at v dd = 6.0v. however, the other minimum and maximum specifications are measured at 2.5v and 5.5v. ? 2008 microchip technology inc. ds11177e-page 3 mcp606/7/8/9 ac characteristics mcp608 chip select characteristics figure 1-1: timing diagram for the cs pin on the mcp608. electrical characteristics: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss =gnd, t a =+25c, v cm =v dd /2, v out v dd /2, v l = v dd /2, r l = 100 k to v l and c l = 60 pf, and cs is tied low (refer to figure 1-2 and figure 1-3 ). parameters sym min typ max units conditions ac response gain bandwidth product gbwp ? 155 ? khz phase margin pm ? 62 ? g = +1 v/v slew rate sr ? 0.08 ? v/s noise input noise voltage e ni ?2.8?v p-p f = 0.1 hz to 10 hz input noise voltage density e ni ?38?nv/ hz f = 1 khz input noise current density i ni ?3?fa/ hz f = 1 khz electrical characteristics: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss =gnd, t a =+25c, v cm =v dd /2, v out v dd /2, v l = v dd /2, r l = 100 k to v l and c l = 60 pf, and cs is tied low (refer to figure 1-2 and figure 1-3 ). parameters sym min typ max units conditions cs low specifications cs logic threshold, low v il v ss ?0.2v dd v cs input current, low i csl -0.1 0.01 ? a cs = 0.2v dd cs high specifications cs logic threshold, high v ih 0.8 v dd ?v dd v cs input current, high i csh ?0.010.1 acs = v dd cs input high, gnd current i ss -2 -0.05 ? a cs = v dd amplifier output leakage, cs high i o(leak) ?10?nacs = v dd cs dynamic specifications cs low to amplifier output turn-on time t on ? 9 100 s cs = 0.2v dd to v out = 0.9 v dd /2, g = +1 v/v, r l = 1 k to v ss cs high to amplifier output hi-z t off ?0.1? scs = 0.8v dd to v out = 0.1 v dd /2, g = +1 v/v, r l = 1 k to v ss cs hysteresis v hyst ?0.6? vv dd = 5.0v cs v out i ss i cs v il v ih t on t off -50 na -50 na -18.7 a -50 na -50 na hi-z hi-z (typical) (typical) (typical) (typical) (typical) mcp606/7/8/9 ds11177e-page 4 ? 2008 microchip technology inc. temperature characteristics 1.1 test circuits the test circuits used for the dc and ac tests are shown in figure 1-2 and figure 1-3 . the bypass capacitors are laid out according to the rules discussed in section 4.5 ?supply bypass? . figure 1-2: ac and dc test circuit for most non-inverting gain conditions. figure 1-3: ac and dc test circuit for most inverting gain conditions. electrical characteristics: unless otherwise indicated, v dd = +2.5v to +5.5v and v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +85 c operating temperature range t a -40 ? +125 c note 1 storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sot23 ja ? 256 ? c/w thermal resistance, 8l-pdip ja ?85?c/w thermal resistance, 8l-soic ja ? 163 ? c/w thermal resistance, 8l-tssop ja ? 124 ? c/w thermal resistance, 14l-pdip ja ?70?c/w thermal resistance, 14l-soic ja ? 120 ? c/w thermal resistance, 14l-tssop ja ? 100 ? c/w note 1: the mcp606/7/8/9 operate over this extended temperature r ange, but with reduced performance. in any case, the junction temperature (t j ) must not exceed the absolute maximum specification of +150c. v dd mcp60x r g r f r n v out v in v dd /2 1f c l r l v l 0.1 f v dd mcp60x r g r f r n v out v dd /2 v in 1f c l r l v l 0.1 f ? 2008 microchip technology inc. ds11177e-page 5 mcp606/7/8/9 2.0 typical performance curves note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =+25c, v cm =v dd /2, v out v dd /2, v l = v dd /2, r l = 100 k to v l , c l = 60 pf, and cs is tied low. figure 2-1: input offset voltage at v dd =5.5v. figure 2-2: input offset voltage at v dd =2.5v. figure 2-3: quiescent current vs. power supply voltage. figure 2-4: input offset voltage drift magnitude at v dd =5.5v. figure 2-5: input offset voltage drift magnitude at v dd =2.5v. figure 2-6: quiescent current vs. ambient temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% 16% -250 -200 -150 -100 -50 0 50 100 150 200 250 input offset voltage (v) percentage of occurances ( ) 1200 samples v dd = 5.5v 0% 2% 4% 6% 8% 10% 12% 14% 16% -250 -200 -150 -100 -50 0 50 100 150 200 250 input offset voltage (v) percentage of occurances ( ) 1200 samples v dd = 2.5v 0 2 4 6 8 10 12 14 16 18 20 22 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) quiescent current per amplifier (a) t a = +85c t a = +25c t a = -40c 0% 2% 4% 6% 8% 10% 12% 14% 16% -8-6-4-202468 input offset voltage drift (v/c) percentage of occurances 206 samples v dd = 5.5v 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% -8 -6 -4 -2 0 2 4 6 8 input offset voltage drift (v/c) percentage of occurances 206 samples v dd = 2.5v 12 14 16 18 20 22 24 -50 -25 0 25 50 75 100 ambient temperature (c) quiescent current per amplifier (a) v dd = 5.5v v dd = 2.5v mcp606/7/8/9 ds11177e-page 6 ? 2008 microchip technology inc. note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =+25c, v cm =v dd /2, v out v dd /2, v l = v dd /2, r l = 100 k to v l , c l = 60 pf, and cs is tied low. figure 2-7: input offset voltage vs. ambient temperature. figure 2-8: open-loop gain and phase vs. frequency. figure 2-9: channel-to-channel separation (mcp607 and mcp609 only). figure 2-10: input offset voltage vs. common mode input voltage. figure 2-11: gain bandwidth product, phase margin vs. ambient temperature. figure 2-12: input noise voltage density vs. frequency. 0 100 200 300 400 500 -50-25 0 255075100 ambient temperature (c) input offset voltage (v) v dd =2.5v v dd = 5.5v representative part -20 0 20 40 60 80 100 120 frequency (hz) open-loop gain (db) -225 -180 -135 -90 -45 0 45 90 open-loop phase () gain phase r l = 25 k ? 0.01 1 0.1 10 1k 100 10k 1m 100k 80 90 100 110 120 130 140 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) channel to channel separation (db) referred to input 100 100k 10k 1k -20 0 20 40 60 80 100 120 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 common mode input voltage (v) input offset voltage (v) t a = +85c t a = +25c t a = -40c v dd = 5.5v 0 20 40 60 80 100 120 140 160 -50 -25 0 25 50 75 100 ambient temperature (c) gain bandwidth product (khz) 0 10 20 30 40 50 60 70 80 phase margin () phase margin gbwp v dd = 5.0v 10 100 1000 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) input noise voltage density (nv/ hz) 0.1 1 10 100 1k 10k 100k ? 2008 microchip technology inc. ds11177e-page 7 mcp606/7/8/9 note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =+25c, v cm =v dd /2, v out v dd /2, v l = v dd /2, r l = 100 k to v l , c l = 60 pf, and cs is tied low. figure 2-13: input bias current, input offset current vs. ambient temperature. figure 2-14: dc open-loop gain vs. load resistance. figure 2-15: cmrr, psrr vs. frequency. figure 2-16: input bias current, input offset current vs. common mode input voltage. figure 2-17: dc open-loop gain vs. power supply voltage. figure 2-18: cmrr, psrr vs. ambient temperature. 0.1 1 10 100 25 30 35 40 45 50 55 60 65 70 75 80 85 ambient temperature (c) input bias and offset currents (pa) i b | i os | v dd = 5.5v v cm = v dd 100 105 110 115 120 125 130 135 1.e+02 1.e+03 1.e+04 1.e+05 load resistance ( ? ) dc open-loop gain (db) v dd = 2.5v v dd = 5.5v 100 100k 10k 1k 0 20 40 60 80 100 120 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 frequency (hz) cmrr and psrr (db) psrr- psrr+ cmrr 0.1 1 10 100 1k 10k -10 0 10 20 30 40 50 60 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input bias and offset currents (pa) i b i os t a = 85c v dd = 5.5v 90 100 110 120 130 140 150 0.00.51.01.52.02.53.03.54.04.55.05.5 power supply voltage (v) dc open-loop gain (db) r l = 25 k ? 75 80 85 90 95 100 -50 -25 0 25 50 75 100 ambient temperature (c) cmrr and psrr (db) cmrr psrr mcp606/7/8/9 ds11177e-page 8 ? 2008 microchip technology inc. note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =+25c, v cm =v dd /2, v out v dd /2, v l = v dd /2, r l = 100 k to v l , c l = 60 pf, and cs is tied low. figure 2-19: output voltage headroom vs. output current magnitude. figure 2-20: maximum output voltage swing vs. frequency. figure 2-21: slew rate vs. ambient temperature. figure 2-22: output voltage headroom vs. ambient temperature at r l =5k . figure 2-23: the mcp606/7/8/9 show no phase reversal. figure 2-24: output short circuit current magnitude vs. ambient temperature. 1 10 100 1000 0.1 1 10 100 output current (ma) output voltage headroom (mv) v dd = 2.5v v dd = 5.5v v dd - v oh v ol - v ss 0.1 1 10 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) maximum output voltage swing (v) v dd = 2.5v 100 100k 10k 1k v dd = 5.5v 0.00 0.02 0.04 0.06 0.08 0.10 0.12 -50 -25 0 25 50 75 100 ambient temperature (c) slew rate (v/s) low to high high to low 0 5 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 ambient temperature (c) output voltage headroom (mv) r l = 5 k 8 v dd = 5.5v v dd = 2.5v v dd - v oh v ol - v ss -1 0 1 2 3 4 5 6 time (100 s/div) input and output voltages (v) v out v in g = +2 v/v v dd = 5.0v 0 5 10 15 20 25 -50-25 0 255075100 ambient temperature (c) output short circuit current magnitude (ma) +i sc , v dd = 2.5v | -i sc |, v dd = 2.5v +i sc , v dd = 5.5v | -i sc |, v dd = 5.5v ? 2008 microchip technology inc. ds11177e-page 9 mcp606/7/8/9 note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =+25c, v cm =v dd /2, v out v dd /2, v l = v dd /2, r l = 100 k to v l , c l = 60 pf, and cs is tied low. figure 2-25: large-signal, non-inverting pulse response. figure 2-26: small-signal, non-inverting pulse response. figure 2-27: chip select (cs ) hysteresis (mcp608 only). figure 2-28: large-signal, inverting pulse response. figure 2-29: small-signal, inverting pulse response. figure 2-30: amplifier output response times vs. chip select (cs ) pulse (mcp608 only). 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (50 s/div) output voltge (v) v dd = 5.0v time (50 s/div) output voltage (20 mv/div) v dd = 5.0v -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.00.51.01.52.02.53.03.54.04.55.0 cs input voltage (v) internal cs switch output (v) amplifier output active amplifier output hi-z v dd = 5.0v hysteresis cs input high to low cs input low to high 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (50 s/div) output voltage (v) v dd = 5.0v time (50 s/div) output voltage (20 mv/div) r l = 25 k ? 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (5 s/div) output voltage (v) -35 -30 -25 -20 -15 -10 -5 0 5 10 15 chip select voltage (v) cs v out output hi-z output hi-z output enabled g = +1 v/v r l = 1 k ? to v ss mcp606/7/8/9 ds11177e-page 10 ? 2008 microchip technology inc. note: unless otherwise indicated, v dd = +2.5v to +5.5v, v ss = gnd, t a =+25c, v cm =v dd /2, v out v dd /2, v l = v dd /2, r l = 100 k to v l , c l = 60 pf, and cs is tied low. figure 2-31: measured input current vs. input voltage (below v ss ). 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input voltage (v) input current magnitude (a) +125c +85c +25c -40c 10m 1m 100 10 1 100n 10n 1n 100p 10p 1p ? 2008 microchip technology inc. ds11177e-page 11 mcp606/7/8/9 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . table 3-1: pin function table. 3.1 analog outputs the output pins are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs are high-impedance cmos inputs with low bias currents. 3.3 chip select digital input the chip select (cs ) pin is a schmitt-triggered, cmos logic input. it is used to place the mcp608 op amp in a low-power mode, with the out put(s) in a hi-z state. 3.4 power supply pins the positive power supply pin (v dd ) is 2.5v to 5.5v higher than the negative power supply pin (v ss ). for normal operation, the out put pins are at voltages between v ss and v dd ; while the input pins are at voltages between v ss ? 0.3v and v dd +0.3v. typically, these parts are used in a single-supply (positive) configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need bypass capacitors . mcp606 mcp607 mcp608 mcp609 symbol description pdip, soic, tssop sot-23-5 61161v out , v outa output (op amp a) 24222v in ?, v ina ? inverting input (op amp a) 33333v in +, v ina + non-inverting input (op amp a) 75474v dd positive power supply ??5?5v inb + non-inverting input (op amp b) ??6?6v inb ? inverting input (op amp b) ??7?7v outb output (op amp b) ????8v outc output (op amp b) ????9v inc ? inverting input (op amp c) ????10v inc + non-inverting input (op amp c) 428411v ss negative power supply ????12v ind + non-inverting input (op amp d) ????13v ind ? inverting input (op amp d) ????14v outd output (op amp d) ???8?cs chip select 1, 5, 8 ? ? 1, 5 ? nc no internal connection mcp606/7/8/9 ds11177e-page 12 ? 2008 microchip technology inc. 4.0 applications information the mcp606/7/8/9 family of op amps is manufactured using microchip?s state-of-the-art cmos process these op amps are unity-gain stable and suitable for a wide range of general purpose applications. 4.1 rail-to-rail inputs 4.1.1 phase reversal the mcp606/7/8/9 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. figure 2-23 shows the input voltage exceed- ing the supply voltage without any phase reversal. 4.1.2 input voltage and current limits the esd protection on the inputs can be depicted as shown in figure 4-1 . this structure was chosen to protect the input transistors, and to minimize input bias current (i b ). the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that go too far above v dd ; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick esd events within the specified limits. figure 4-1: simplified analog input esd structures. in order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the currents and voltages at the v in + and v in ? pins (see absolute maximum ratings ? at the beginning of section 1.0 ?electri cal characteristics? ). figure 4-2 shows the recommended approach to protecting these inputs. the internal esd diodes prevent the input pins (v in + and v in ?) from going too far below ground, and the resistors r 1 and r 2 limit the possible current drawn out of the input pins. diodes d 1 and d 2 prevent the input pins (v in + and v in ?) from going too far above v dd , and dump any currents onto v dd . when implemented as shown, resistors r 1 and r 2 also limit the current through d 1 and d 2 . figure 4-2: protecting the analog inputs. it is also possible to connect the diodes to the left of resistors r 1 and r 2 . in this case, current through the diodes d 1 and d 2 needs to be limited by some other mechanism. the resistors th en serve as in-rush current limiters; the dc current into the input pins (v in + and v in ?) should be very small. a significant amount of current can flow out of the inputs when the common mode voltage (v cm ) is below ground (v ss ); see figure 2-31 . applications that are high impedance may need to limit the useable voltage range. 4.1.3 normal operation the input stage of the mcp606/7/8/9 op amps use a pmos input stage. it operates at low common mode input voltage (v cm ), including ground. with this topology, the device operates with v cm up to v dd ?1.1v and 0.3v below v ss . figure 4-3 shows a unity gain buffer. since v out is the same voltage as the inverting input, v out must be kept below v dd ?1.2v for correct operation. figure 4-3: unity gain buffer has a limited v out range. bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in ? v 1 mcp60x r 1 v dd d 1 r 1 > v ss ? (minimum expected v 1 ) 2ma r 2 > v ss ? (minimum expected v 2 ) 2ma v 2 r 2 d 2 r 3 mcp60x v out + ? v in ? 2008 microchip technology inc. ds11177e-page 13 mcp606/7/8/9 4.2 rail-to-rail output there are two specificat ions that describe the output-swing capability of t he mcp606/7/8/9 family of op amps. the first specification (maximum output voltage swing) defines the absolute maximum swing that can be achieved under the specified load conditions. for instance, the output voltage swings to within 15 mv of the negative rail with a 25 k load to v dd /2. figure 2-23 shows how the output voltage is limited when the input goes beyond the linear region of operation. the second specification that describes the out- put-swing capability of these amplifiers (linear output voltage range) defines the maximum output swing that can be achieved while the amplifier still operates in its linear region. to verify linear operation in this range, the large-signal dc open-loop gain (a ol ) is measured at points inside the supply rails. the measurement must meet the specified a ol conditions in the specification table. 4.3 capacitive loads driving large capacitive loads can cause stability problems for voltage-feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain-peaking in the frequency response, with overshoot and ringing in the step response. a unity-gain buffer (g = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. when driving large capacitive loads with these op amps (e.g., > 60 pf when g = +1), a small series resistor at the output (r iso in figure 4-4 ) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-4: output resistor, r iso stabilizes large capacitive loads. figure 4-5 gives recommended r iso values for different capacitive loads and gains. the x-axis is the normalized load capacitance (c l /g n ), where g n is the circuit?s noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -1 v/v gives g n =+2v/v). figure 4-5: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double-check the resulting frequency response peaking and step response overshoot. modify r iso ?s value until the response is reasonable. bench evaluation and simula- tions with the mcp606/7/8/9 spice macro model are helpful. 4.4 mcp608 chip select the mcp608 is a single op amp with chip select (cs ). when cs is pulled high, the supply current drops to 50 na (typical) and flows through the cs pin to v ss . when this happens, the amplifier output is put into a high-impedance state. by pulling cs low, the amplifier is enabled. the cs pin has an internal 5 m (typical) pull-down resistor connected to v ss , so it will go low if the cs pins is left floating. figure 1-1 shows the output voltage and supply current response to a cs pulse. 4.5 supply bypass with this family of operat ional amplifiers, the power supply pin (v dd for single-supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good high-frequency performance. it also needs a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with other nearby analog parts. 4.6 unused op amps an unused op amp in a quad package (mcp609) should be configured as shown in figure 4-6 . these circuits prevent the output from toggling and causing crosstalk. circuits a sets the op amp at its minimum noise gain. the resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. circuit b uses the minimum number of components and operates as a comparator, but it may draw more current. v in mcp60x r iso v out c l 100 1000 10000 10 100 1000 10000 normalized load capacitance; c l /g n (f) recommended r iso ( ? ) 10p 10n 1n 100p 100 10k 1k g n = +1 g n = +2 g n +4 mcp606/7/8/9 ds11177e-page 14 ? 2008 microchip technology inc. figure 4-6: unused op amps. 4.7 pcb surface leakage in applications where low input bias current is critical, printed circuit board (pcb) surface-leakage effects need to be considered. surface leakage is caused by humidity, dust or other contamination on the board. under low humidity conditions, a typical resistance between nearby traces is 10 12 . a 5v difference would cause 5 pa of current to flow, which is greater than the mcp606/7/8/9 family?s bias current at 25c (1 pa, typi- cal). the easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). the guard ring is biased at the same voltage as the sensitive pin. an example of this type of layout is shown in figure 4-7 . figure 4-7: example guard ring layout for inverting gain. 1. non-inverting gain and unity-gain buffer: a) connect the non-inverting pin (v in +) to the input with a wire that does not touch the pcb surface. b) connect the guard ring to the inverting input pin (v in ?). this biases the guard ring to the common mode input voltage. 2. inverting gain and transimpedance gain (convert current to voltage, such as photo detectors) amplifiers: a) connect the guard ring to the non-inverting input pin (v in +). this biases the guard ring to the same reference voltage as the op amp (e.g., v dd /2 or ground). b) connect the inverting pin (v in ?) to the input with a wire that does not touch the pcb surface. 4.8 application circuits 4.8.1 low-side battery current sensor the mcp606/7/8/9 op amps can be used to sense the load current on the low-side of a battery using the circuit in figure 4-8 . in this circuit, the current from the power supply (minus the current required to power the mcp606) flows through a sense resistor (r sen ), which converts it to voltage. this is gained by the the amplifier and resistors, r g and r f . since the non-inverting input of the amplifier is at t he load?s negative supply (v lm ), the gain from r sen to v out is r f /r g . figure 4-8: low side battery current sensor. since the input bias current and input offset voltage of the mcp606 are low, and the input is capable of swing- ing below ground, there is ve ry little error generated by the amplifier. the quiescent current is very low, which helps conserve battery power. the rail-to-rail output makes it possible to read very low currents. v dd v dd ? mcp604 (a) ? mcp604 (b) r 1 r 2 v dd v ref v ref v dd r 2 r 1 r 2 + ------------------ ? = guard ring v ss v in -v in + v out v lm i + l r sen r f r g ? () = r f to load 2.5v r g mcp606 5k 50 k to load v out r sen 10 (v lm ) (v lp ) i l to 6.0v ? 2008 microchip technology inc. ds11177e-page 15 mcp606/7/8/9 4.8.2 photodiod e amplifiers sensors that produce an output current and have high output impedance can be connected to a transimped- ance amplifier. the transi mpedance amplifier converts the current into voltage. photodiodes are one sensor that produce an output current. the key op amp characteristics that are needed for these circuits are: low input offset voltage, low input bias current, high input impedance and an input common mode range that includes ground. the low input offset voltage and low input bias current support a very low voltage drop across the photodiode; this gives the best photodiode linearity. since the photodiode is biased at ground, the op amp?s input needs to function well both above and below ground. 4.8.2.1 photo-voltaic mode figure 4-9 shows a transimpedance amplifier with a photodiode (d 1 ) biased in the photo-voltaic mode (0v across d 1 ), which is used for precision photodiode sensing. as light impinges on d 1 , charge is generated, causing a current to flow in the reverse bias direction of d 1 . the op amp?s negative feedback forces the voltage across the d 1 to be nearly 0v. resistor r 2 converts the current into voltage. capacitor c 2 limits the bandwidth and helps stabilize the circuit when d 1 ?s junction capacitance is large. figure 4-9: photodiode (in photo-voltaic mode) and transimpedance amplifier. 4.8.2.2 photo-conductive mode figure 4-9 shows a transimpedance amplifier with a photodiode (d 1 ) biased in the photo-conductive mode (d 1 is reverse biased), which is used for high-speed applications. as light impinges on d 1 , charge is generated, causing a current to flow in the reverse bias direction of d 1 . placing a negative bias on d 1 significantly reduces its junction capacitance, which allows the circuit to operate at a much higher speed. this reverse bias also increases the dark current and current noise, however. resistor r 2 converts the current in to voltage. capacitor c 2 limits the bandwidth and helps stabilize the circuit when d 1 ?s junction capacitance is large. figure 4-10: photodiode (in photo-conductive mode) and transimpedance amplifier. 4.8.3 two op amp instrumentation amplifier the two op amp instrumentation amplifier shown in figure 4-11 serves the function of taking the difference of two input voltages, level-shifting it and gaining it to the output. this configuratio n is best suited for higher gains (i.e., gain > 3 v/v). the reference voltage (v ref ) is typically at mid-supply (v dd /2) in a single-supply environment. figure 4-11: two op amp instrumentation amplifier. the key specifications t hat make the mcp606/7/8/9 family appropriate for this application circuit are low input bias current, low offset voltage and high com- mon-mode rejection. v out i d 1 r 2 = r 2 d 1 mcp606 v out light c 2 v dd i d1 v out i d 1 r 2 = r 2 d 1 mcp606 v out light c 2 v dd i d1 vb v b 0 < v out v 1 v 2 ? () 1 r 1 r 2 ------ 2r 1 r g --------- - ++ ?? ?? ?? v ref + = r 2 r 1 mcp607 v out v 2 v ref ? r 1 r 2 v 1 r g mcp607 ? mcp606/7/8/9 ds11177e-page 16 ? 2008 microchip technology inc. 4.8.4 three op amp instrumentation amplifier a classic, three op amp instrumentation amplifier is illustrated in figure 4-12 . the two input op amps pro- vide differential signal gain and a common mode gain of +1. the output op amp is a difference amplifier, which converts its input signal from differential to a sin- gle ended output; it rejects common mode signals at its input. the gain of this circuit is simply adjusted with one resistor (r g ). the reference voltage (v ref ) is typically referenced to mid-supply (v dd /2) in single-supply applications. figure 4-12: three op amp instrumentation amplifier. 4.8.5 precision gain with good load isolation in figure 4-13 , the mcp606 op amps, r 1 and r 2 provide a high gain to the input signal (v in ). the mcp606?s low offset voltage makes this an accurate circuit. the mcp601 is configured as a unity-gain buffer. it isolates the mcp606?s output from the load, increasing the high-gain stage?s precis ion. since the mcp601 has a higher output current, with the two amplifiers being housed in separate packages, there is minimal change in the mcp606?s offset voltage due to loading effect. figure 4-13: precision gain with good load isolation. v out v 1 v 2 ? () 1 2r 2 r g --------- + ?? ?? ?? r 4 r 3 ----- - ?? ?? ?? v ref + = r 2 mcp607 v ref v 1 ? r 4 r 3 mcp606 r 2 r g mcp607 v out v 2 ? r 4 r 3 v out v in 1r 2 r 1 ? + () = r 2 r 1 mcp606 v out v in mcp601 ? 2008 microchip technology inc. ds11177e-page 17 mcp606/7/8/9 5.0 design aids microchip provides the basic design tools needed for the mcp606/7/8/9 fam ily of op amps. 5.1 spice macro model the latest spice macro model for the mcp606/7/8/9 op amps is available on the microchip web site at www.microchip.com. this model is intended to be an initial design tool that works well in the op amp?s linear region of operation over t he temperature range. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchip?s filterlab ? software is an innovative software tool that simplifies analog active filter (using op amps) design. available at no cost from the microchip web site at www.m icrochip.com/filterlab, the filterlab design tool prov ides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance. 5.3 mindi? circuit designer & simulator microchip?s mindi? circuit designer & simulator aids in the design of various circuits useful for active filter, amplifier and power-management applications. it is a free online circuit designer & simulator available from the microchip web site at www.microchip.com/mindi. this interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simulate circuits. circuits developed using the mindi circuit designer & simulator can be downloaded to a personal computer or workstation. 5.4 maps (microchip advanced part selector) maps is a software tool that helps semiconductor professionals efficiently id entify microchip devices that fit a particular design requirement. available at no cost from the microchip website at www.microchip.com/ maps, the maps is an overall selection tool for microchip?s product portfolio that includes analog, memory, mcus and dscs. using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparasion reports. helpful links are also provided for datasheets, purchase, and sampling of microchip parts. 5.5 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demonstration and evaluat ion boards that are designed to help you achieve faster time to market. for a complete listing of these boards and their corresponding user?s guides and technical information, visit the microchip web si te at www.microchip.com/ analogtools. two of our boards that are especially useful are: ? p/n soic8ev: 8-pin soic/msop/tssop/dip evaluation board ? p/n soic14ev: 14-pin soic/tssop/dip evalu- ation board 5.6 application notes the following microchip application notes are avail- able on the microchip web site at www.microchip. com/ appnotes and are recommended as supplemental ref- erence resources. adn003: ?select the right operational amplifier for your filtering circuits?, ds21821 an722: ?operational amplifier topologies and dc specifications?, ds00722 an723: ?operational amplifier ac specifications and applications?, ds00723 an884: ?driving capacitive loads with op amps?, ds00884 an990: ?analog sensor conditioning circuits ? an overview?, ds00990 these application notes and others are listed in the design guide: ?signal chain design guide?, ds21825 mcp606/7/8/9 ds11177e-page 18 ? 2008 microchip technology inc. 6.0 packaging information 6.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 5-lead sot-23 ( mcp606 ) example: xxnn sb25 xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example : 8-lead soic (150 mil) example : xxxxxxxx xxxxyyww nnn mcp606 i/p256 0722 mcp606 i/sn0722 256 mcp606 i/p 256 0810 mcp606 i sn 0810 256 3 e or or 3 e 8-lead tssop example: xxxx yyww nnn 606 i810 256 ? 2008 microchip technology inc. ds11177e-page 19 mcp606/7/8/9 package marking information (continued) 14-lead tssop ( mcp609 ) example: xxxxxxxx yyww nnn 609ist 0545 256 14-lead pdip (300 mil) ( mcp609 )example : xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn mcp609 -i/p 0722256 mcp609 0810256 i/p 3 e or 14-lead soic (150 mil) ( mcp609 ) example: xxxxxxxxxx yywwnnn xxxxxxxxxx mcp609isl 0722256 mcp609 0810256 i/sl ^^ or 3 e mcp606/7/8/9 ds11177e-page 20 ? 2008 microchip technology inc. ! " #$ " % & ' ( ( ) * ( + , * $--((( - * . /00/%1 0 /2 23 4 25 , 2 ! 0 , 6! " # 3 0 , 6 " # 3' 7 6 8 ! , * %* 96 8 : 8 ! 3' ; 8 : , * ; : 8 9 3' 0 8 : ) 0 0 8 < ) 0 :! 8 9 ) = 8 := 0 %* 9 8 < 0 ; 5 8 ! n b e e1 d 1 2 3 e e1 a a1 a2 c l l1 % & ( # >6" ? 2008 microchip technology inc. ds11177e-page 21 mcp606/7/8/9 ! "## $% ! , ' & ' &+ 5 5 ( ? # : @ ! " #$ " % & ' ( ( ) * ( + , * $--((( - * . /2#7 0 /2 23 4 25 , 2 9 , " # % , 8 8 , * %* ! : 6! " , ! 8 8 ; 6 : :! , * ; ! 9 3' 0 : 9 : , 0 ! : ! 0 %* 9 ! . 0 ; 5 < 0 ( 0 ; 5 9 3' 1 ( ? " 8 8 : n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c % & ( # >9" mcp606/7/8/9 ds11177e-page 22 ? 2008 microchip technology inc. " &'()#$%!* , ' & ' &+ 5 5 ( ? # : ! ! " #$ " % & ' ( ( 1)$ 1 + & ( + & ) * ( + , * $--((( - * . /00/%1 0 /2 23 4 25 , 2 9 , " # 3' 7 8 8 ! , * %* ! 8 8 ? 8 ! 3' ; < " # , * ; :6 " # 3' 0 6 " # # a b ! 8 ! ) 0 0 8 ) 0 1) ) = 8 9= 0 %* 8 ! 0 ; 5 : 8 ! % != 8 != " != 8 != d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h % & ( # >!" ? 2008 microchip technology inc. ds11177e-page 23 mcp606/7/8/9 " &'()#$%!* ) * ( + , * $--((( - * + + , "-(-$% , ' & ' &+ 5 5 ( ! : ! " #$ " % & ' ( ( 1)$ 1 + & ( + & ) * ( + , * $--((( - * . /00/%1 0 /2 23 4 25 , 2 9 , , * %* 9 ! ! 8 ! 3' ; < " # , * ; : ! , * 0 6 : : ) 0 0 ! < ! ) 0 1) ) = 8 9= 0 %* 6 8 0 ; 5 6 8 : d n e e1 note 1 12 b e c a a1 a2 l1 l % & ( # >9<" mcp606/7/8/9 ds11177e-page 24 ? 2008 microchip technology inc. .- ! "## $% ! , ' & ' &+ 5 5 ( ? # : @ ! " #$ " % & ' ( ( ) * ( + , * $--((( - * . /2#7 0 /2 23 4 25 , 2 , " # % , 8 8 , * %* ! : 6! " , ! 8 8 ; 6 : :! , * ; ! 9 3' 0 :! ! ! % , 0 ! : ! 0 %* 9 ! . 0 ; 5 ! < 0 ( 0 ; 5 9 3' 1 ( ? " 8 8 : n e1 d note 1 12 3 e c eb a2 l a a1 b1 be % & ( # >!" ? 2008 microchip technology inc. ds11177e-page 25 mcp606/7/8/9 .- " &'()#$%!* , ' & ' &+ 5 5 ( ? # : ! ! " #$ " % & ' ( ( 1)$ 1 + & ( + & ) * ( + , * $--((( - * . /00/%1 0 /2 23 4 25 , 2 , " # 3' 7 8 8 ! , * %* ! 8 8 ? 8 ! 3' ; < " # , * ; :6 " # 3' 0 9 b ! 8 ! ) 0 0 8 ) 0 1) ) = 8 9= 0 %* 8 ! 0 ; 5 : 8 ! % != 8 != " != 8 != note 1 n d e e1 1 23 b e a a1 a2 l l1 c h h % & ( # > mcp606/7/8/9 ds11177e-page 26 ? 2008 microchip technology inc. .- + + , "-(-$% , ' & ' &+ 5 5 ( ! : ! " #$ " % & ' ( ( 1)$ 1 + & ( + & ) * ( + , * $--((( - * . /00/%1 0 /2 23 4 25 , 2 , , * %* 9 ! ! 8 ! 3' ; < " # , * ; : ! , * 0 6 ! ! ) 0 0 ! < ! ) 0 1) ) = 8 9= 0 %* 6 8 0 ; 5 6 8 : note 1 d n e e1 1 2 e b c a a1 a2 l1 l % & ( # >9" ? 2008 microchip technology inc. ds11177e-page 25 mcp606/7/8/9 appendix a: revision history revision e (march 2008) the following is the list of modifications: 1. increased maximum operating v dd . 2. added test circuits. 3. updated performance curves. 4. added figure 2-31 . 5. added section 4.1.1 ?phase reversal? , section 4.1.2 ?input voltage and current limits? , ad section 4.1.3 ?normal opera- tion? . 6. updated section 5.0 ?design aids? 7. updated section 6.0 ?packaging informa- tion? . updated package outline drawings. revision d (february 2005) the following is the list of modifications: 1. added section 3.0 ?pin descriptions? . 2. updated section 4.0 ?applications information? . 3. added section 4.3 ?capacitive loads? 4. updated section 5.0 ?design aids? to include filterlab ? and to point to the latest spice macro model. 5. corrected and updated section 6.0 ?packaging information? . 6. added appendix a: ?revision history? . revision c (january 2001) ? undocumented changes revision b (may 2000) ? undocumented changes revision a (january 2000) ? original release of this document. mcp606/7/8/9 ds11177e-page 26 ? 2008 microchip technology inc. notes: ? 2008 microchip technology inc. ds11177e-page 27 mcp606/7/8/9 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device mcp606 = single op amp mcp606t = single op amp tape and reel (soic, tssop) mcp607 = dual op amp mcp607t = dual op amp tape and reel (soic, tssop) mcp608 = single op amp with cs mcp608t = single op amp with cs tape and reel (soic, tssop) mcp609 = quad op amp mcp609t = quad op amp tape and reel (soic, tssop) temperature range i = -40 c to +85 c package ot = plastic sot-23, 5-lead p = plastic dip (300 mil body), 8-lead, 14-lead sn = plastic soic (3.90 mm body), 8-lead sl = plastic soic (3.90 mm body), 14-lead st = plastic tssop, 8-lead, 14-lead part no. x /xx package temperature range device examples: a) mcp606-i/p: industrial temperature, 8ld pdip package. b) mcp606-i/sn: industrial temperature, 8ld soic package. c) mcp606t-i/sn: tape and reel, industrial temperature, 8ld soic package. d) mcp606-i/st: industrial temperature, 8ld tssop package. e) mcp606t-i/ot: tape and reel, industrial temperature, 5ld sot-23 package. a) mcp607-i/p: industrial temperature, 8ld pdip package. b) mcp607t-i/sn: tape and reel, c) industrial temperature, 8ld soic package. a) mcp608-i/sn: industrial temperature, 8ld soic package. b) mcp608t-i/sn: tape and reel, industrial temperature, 8ld soic package. a) mcp609-i/p: industrial temperature, 14ld pdip package. b) mcp609t-i/sl: tape and reel, c) industrial temperature, 14ld soic package. mcp606/7/8/9 ds11177e-page 28 ? 2008 microchip technology inc. notes: ? 2008 microchip technology inc. ds11177e-page 29 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microchip te chnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, a pplication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds11177e-page 30 ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/02/08 |
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